ARM Cortex-A53 MPCore - Aarch32 Debug Register Summary

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-15
ID021414 Non-Confidential
11.5 AArch32 debug register summary
Table 11-7 summarizes the 32-bit and 64-bit debug control registers that are accessible in the
AArch32 Execution state from the internal CP14 interface. These registers are accessed by the
MCR and MRC instructions in the order of CRn, op2, CRm, Op1 or MCRR and MRRC instructions in the
order of CRm, Op1. For those registers not described in this chapter, see the ARM
®
Architecture
Reference Manual ARMv8, for ARMv8-A architecture profile.
See the Memory-mapped register summary on page 11-21 for a complete list of registers
accessible from the internal memory-mapped and the external debug interface.
Table 11-7 AArch32 debug register summary
Offset CRn Op2 CRm Op1 Name Type Description
- c0 0 c0 0 DBGDIDR RO Debug ID Register on page 11-17
- c0 0 c1 0 DBGDSCRint RO Debug Status and Control Register, Internal View
- c0 0 c2 0 DBGDCCINT RW Debug Comms Channel Interrupt Enable Register
0x08C c0 0 c5 0 DBGDTRTXint WO Debug Data Transfer Register, Transmit, Internal View
DBGDTRRXint RO Debug Data Transfer Register, Receive, Internal View
-c00c60
DBGWFAR
a
RW Watchpoint Fault Address Register, RES0
- c0 0 c7 0 DBGVCR RW Debug Vector Catch Register
- c0 2 c0 0 DBGDTRRXext RW Debug Data Transfer Register, Receive, External View
- c0 2 c2 0 DBGDSCRext RW Debug Status and Control Register, External View
- c0 2 c3 0 DBGDTRTXext RW Debug Data Transfer Register, Transmit, External
View
0x098 c0 2 c6 0 DBGOSECCR RW Debug OS Lock Exception Catch Control Register
0x400 c0 4 c0 0 DBGBVR0 RW Debug Breakpoint Value Register 0
0x410 c0 4 c1 0 DBGBVR1 RW Debug Breakpoint Value Register 1
0x420 c0 4 c2 0 DBGBVR2 RW Debug Breakpoint Value Register 2
0x430 c0 4 c3 0 DBGBVR3 RW Debug Breakpoint Value Register 3
0x440 c0 4 c4 0 DBGBVR4 RW Debug Breakpoint Value Register 4
0x450 c0 4 c5 0 DBGBVR5 RW Debug Breakpoint Value Register 5
0x408 c0 5 c0 0 DBGBCR0 RW Debug Breakpoint Control Registers, EL1 on
page 11-8
0x418 c0 5 c1 0 DBGBCR1 RW Debug Breakpoint Control Registers, EL1 on
page 11-8
0x428 c0 5 c2 0 DBGBCR2 RW Debug Breakpoint Control Registers, EL1 on
page 11-8
0x438 c0 5 c3 0 DBGBCR3 RW Debug Breakpoint Control Registers, EL1 on
page 11-8
0x448 c0 5 c4 0 DBGBCR4 RW Debug Breakpoint Control Registers, EL1 on
page 11-8