ARM Cortex-A53 MPCore - Optional Integrated L2 Cache

Level 2 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-18
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7.6 Optional integrated L2 cache
The optional integrated L2 configurable caches sizes are 128KB, 256KB, 512KB, 1MB, and
2MB.
Data is allocated to the L2 cache only when evicted from the L1 memory system, not when first
fetched from the system. The only exceptions to this rule are for memory marked with the inner
transient hint, or for non-temporal loads, see Non-temporal loads on page 6-12, that are only
ever allocated to the L2 cache. The L1 cache can prefetch data from the system, without data
being evicted from the L2 cache.
Instructions are allocated to the L2 cache when fetched from the system and can be invalidated
during maintenance operations.
The L2 cache is 16-way set associative. The L2 cache tags are looked up in parallel with the
SCU duplicate tags. If both the L2 tag and SCU duplicate tag hit, a read accesses the L2 cache
in preference to snooping one of the other cores.
L2 RAMs are invalidated automatically at reset unless the L2RSTDISABLE signal is set HIGH
when the nL2RESET signal is deasserted.
7.6.1 External aborts handling
The L2 memory system handles two types of external abort depending on the attributes of the
memory region of the access:
• All load accesses use the synchronous abort mechanism.
• All
STREX , STREXB , STREXH , STREXD , STXR , STXRB , STXRH , STXP , STLXR , STLXRB , STLXRH and STLXP
instructions use the synchronous abort mechanism.
• All store accesses to Device memory, or Normal memory that is Inner Non-cacheable,
Inner Write-Through, Outer Non-cacheable, or Outer Write-Through use the
asynchronous abort mechanism, except for
STREX , STREXB , STREXH , STREXD , STXR , STXRB ,
STXRH , STXP , STLXR , STLXRB , STLXRH , and STLXP .
• All store accesses to Normal memory that is both Inner Cacheable and Outer Cacheable
and any evictions from L1 or L2 cache do not cause an abort in the processor, instead they
assert the nEXTERRIRQ pin. This is because the access that aborts might not relate
directly back to a specific core in the cluster.
• L2 linefills triggered by an L1 Instruction fetch assert the nEXTERRIRQ pin if the data
is received from the interconnect in a dirty state. Instruction data can be marked as dirty
as a result of self-modifying code or a line containing a mixture of data and instructions.
If an error response is received on any part of the line, the dirty data might be lost.
• DVM operations that receive an error response use the asynchronous abort mechanism.
Note
When nEXTERRIRQ is asserted it remains asserted until the error is cleared by a write of 0 to
the AXI or CHI asynchronous error bit of the L2ECTLR register.