ARM Cortex-A53 MPCore - Aarch32 PMU Register Summary

Performance Monitor Unit
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12.5 AArch32 PMU register summary
The PMU counters and their associated control registers are accessible in the AArch32
Execution state from the internal CP15 system register interface with
MCR and MRC instructions
for 32-bit registers and
MCRR and MRRC for 64-bit registers.
Table 12-9 gives a summary of the Cortex-A53 PMU registers in the AArch32 Execution state.
For those registers not described in this chapter, see the ARM
®
Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile.
See the Memory-mapped register summary on page 12-23 for a complete list of registers that
are accessible from the internal memory-mapped interface or the external debug interface.
Table 12-9 PMU register summary in the AArch32 Execution state
CRn Op1 CRm Op2 Name Type Width Description
c9 0 c12 0 PMCR RW 32 Performance Monitors Control Register on page 12-16
c9 0 c12 1 PMCNTENSET RW 32 Performance Monitors Count Enable Set Register
c9 0 c12 2 PMCNTENCLR RW 32 Performance Monitors Count Enable Clear Register
c9 0 c12 3 PMOVSR RW 32 Performance Monitors Overflow Flag Status Register
c9 0 c12 4 PMSWINC WO 32 Performance Monitors Software Increment Register
c9 0 c12 5 PMSELR RW 32 Performance Monitors Event Counter Selection Register
c9 0 c12 6 PMCEID0 RO 32 Performance Monitors Common Event Identification
Register 0 on page 12-18
c9 0 c12 7 PMCEID1 RO 32 Performance Monitors Common Event Identification
Register 1 on page 12-21
c9 0 c13 0 PMCCNTR[31:0] RW 32 Performance Monitors Cycle Count Register
- 0 c9 - PMCCNTR[63:0] RW 64
c9 0 c13 1 PMXEVTYPER RW 32 Performance Monitors Selected Event Type Register
PMCCFILTR RW 32 Performance Monitors Cycle Count Filter Register
c9 0 c13 2 PMXEVCNTR RW 32 Performance Monitors Selected Event Count Register
c9 0 c14 0 PMUSERENR RW 32 Performance Monitors User Enable Register
c9 0 c14 1 PMINTENSET RW 32 Performance Monitors Interrupt Enable Set Register
c9 0 c14 2 PMINTENCLR RW 32 Performance Monitors Interrupt Enable Clear Register
c9 0 c14 3 PMOVSSET RW 32 Performance Monitor Overflow Flag Status Set Register
c14 0 c8 0 PMEVCNTR0 RW 32 Performance Monitor Event Count Registers
c14 0 c8 1 PMEVCNTR1 RW 32
c14 0 c8 2 PMEVCNTR2 RW 32
c14 0 c8 3 PMEVCNTR3 RW 32
c14 0 c8 4 PMEVCNTR4 RW 32
c14 0 c8 5 PMEVCNTR5 RW 32