ARM Cortex-A53 MPCore - Chapter 6 Level 1 Memory System; About the L1 Memory System

Level 1 Memory System
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6.1 About the L1 memory system
The L1 memory system consists of separate instruction and data caches. The implementer
configures the instruction and data caches independently during implementation, to sizes of
8KB, 16KB, 32KB, or 64KB.
The L1 Instruction memory system has the following key features:
• Instruction side cache line length of 64 bytes.
• 2-way set associative L1 Instruction cache.
• 128-bit read interface to the L2 memory system.
The L1 Data memory system has the following features:
• Data side cache line length of 64 bytes.
• 4-way set associative L1 Data cache.
• 256-bit write interface to the L2 memory system.
• 128-bit read interface to the L2 memory system.
• Read buffer that services the Data Cache Unit (DCU), the Instruction Fetch Unit (IFU)
and the TLB.
• 64-bit read path from the data L1 memory system to the datapath.
• 128-bit write path from the datapath to the L1 memory system.
• Support for three outstanding data cache misses.
• Merging store buffer capability. This handles writes to:
— Device memory.
— Normal Cacheable memory.
— Normal Non-cacheable memory.
• Data side prefetch engine.