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ARM Cortex-A53 MPCore - Page 345

ARM Cortex-A53 MPCore
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ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-1
ID021414 Non-Confidential
Chapter 6
Level 1 Memory System
This chapter describes the L1 memory system. It contains the following sections:
About the L1 memory system on page 6-2.
Cache behavior on page 6-3.
Support for v8 memory types on page 6-6.
L1 Instruction memory system on page 6-7.
L1 Data memory system on page 6-9.
Data prefetching on page 6-12.
Direct access to internal memory on page 6-13.

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