Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-40
ID021414 Non-Confidential
12.10 Interrupts
The Cortex-A53 processor asserts the nPMUIRQ signal when an interrupt is generated by the
PMU. You can route this signal to an external interrupt controller for prioritization and masking.
This is the only mechanism that signals this interrupt to the processor.
This interrupt is also driven as a trigger input to the CTI. See Chapter 14 Cross Trigger for more
information.
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