EasyManua.ls Logo

ARM Cortex-A53 MPCore - Page 493

ARM Cortex-A53 MPCore
635 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-39
ID021414 Non-Confidential
0xE8
- - - Attributable Performance Impact Event.
Counts every cycle there is a stall in the
Wr stage because of a store.
- - [8] [8] Two instructions architecturally
executed.
Counts every cycle in which two
instructions are architecturally retired.
Event 0x08, INTR_RETIRED, always
counts when this event counts.
- - [26] [26] L2 (data or tag) memory error,
correctable or non-correctable.
- - [27] [27] SCU snoop filter memory error,
correctable or non-correctable.
- - [28] - Advanced SIMD and Floating-point
retention active.
- - [29] - CPU retention active.
Table 12-28 PMU events (continued)
Event
number
Event mnemonic
PMU event bus
(to external)
PMU event bus
(to trace)
Event name

Table of Contents

Related product manuals