ARM Cortex-A53 MPCore - Aarch32 Register Descriptions

System Control
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4.5 AArch32 register descriptions
This section describes all the CP15 system registers in register number order. Table 4-122 on
page 4-137 to Table 4-136 on page 4-147 provide cross-references to individual registers.
4.5.1 Main ID Register
The MIDR characteristics are:
Purpose Provides identification information for the processor, including an
implementer code for the device and a device ID number.
Usage constraints This register is accessible as follows:
Configurations The MIDR is:
• Architecturally mapped to the AArch64 MIDR_EL1 register. See
Multiprocessor Affinity Register on page 4-15.
• Architecturally mapped to external MIDR_EL1 register.
Attributes MIDR is a 32-bit register.
Figure 4-76 shows the MIDR bit assignments.
Figure 4-76 MIDR bit assignments
Table 4-148 shows the MIDR bit assignments.
To access the MIDR:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
VariantImplementer
31 23 20 19 16 15 4 3 0
Architecture PartNum Revision
24
Table 4-148 MIDR bit assignments
Bits Name Function
[31:24] Implementer Indicates the implementer code. This value is:
0x41 ASCII character 'A' - implementer is ARM Limited.
[23:20] Variant Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn
description of the product revision status. This value is:
0x0 r0p2.
[19:16] Architecture Indicates the architecture code. This value is:
0xF Defined by CPUID scheme.
[15:4] PartNum Indicates the primary part number. This value is:
0xD03 Cortex-A53 processor.
[3:0] Revision Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of
the rnpn description of the product revision status. This value is:
0x2 r0p2.