System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-158
ID021414 Non-Confidential
MRC p15, 0, <Rt>, c0, c0, 0; Read MIDR into Rt
Register access is encoded as follows:
The MIDR can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xD00
.
4.5.2 Multiprocessor Affinity Register
The MPIDR characteristics are:
Purpose Provides an additional core identification mechanism for scheduling
purposes in a cluster.
EDDEVAFF0 is a read-only copy of MPIDR accessible from the external
debug interface.
Usage constraints This register is accessible as follows:
Configurations The MPIDR is:
• Architecturally mapped to the AArch64 MPIDR_EL1[31:0]
register. See Multiprocessor Affinity Register on page 4-15.
• Architecturally mapped to external EDDEVAFF0 register.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes MPIDR is a 32-bit register.
Figure 4-77 shows the MPIDR bit assignments.
Figure 4-77 MPIDR bit assignments
Table 4-149 MPIDR access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0000 000
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
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