Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-10
ID021414 Non-Confidential
13.7 ETM register summary
This section summarizes the ETM trace unit registers. For full descriptions of the ETM trace
unit registers, see:
• ETM register descriptions on page 13-13, for the
IMPLEMENTATION DEFINED registers and
the ARM
®
ETM
™
Architecture Specification, ETMv4, for the other registers.
In Table 13-3, access type is described as follows:
RW Read and write.
RO Read only.
WO Write only.
Table 13-3 lists all of the ETM trace unit registers.
All ETM trace unit registers are 32 bits wide. The description of each register includes its offset
from a base address. The base address is defined by the system integrator when placing the ETM
trace unit in the Debug-APB memory map.
Table 13-3 ETM trace unit register summary
Name Type Description
--Reserved
TRCPRGCTLR RW Programming Control Register on page 13-13
TRCSTATR RO Status Register on page 13-13
TRCCONFIGR RW Trace Configuration Register on page 13-14
TRCAUXCTLR RW Auxiliary Control Register on page 13-16
TRCEVENTCTL0R RW Event Control 0 Register on page 13-18
TRCEVENTCTL1R RW Event Control 1 Register on page 13-19
TRCSTALLCTLR RW Stall Control Register on page 13-20
TRCTSCTLR RW Global Timestamp Control Register on page 13-21
TRCSYNCPR RW Synchronization Period Register on page 13-22
TRCCCCTLR RW Cycle Count Control Register on page 13-23
TRCBBCTLR RW Branch Broadcast Control Register on page 13-15
TRCTRACEIDR RW Trace ID Register on page 13-23
TRCVICTLR RW ViewInst Main Control Register on page 13-24
TRCVIIECTLR RW ViewInst Include-Exclude Control Register on page 13-26
TRCVISSCTLR RW ViewInst Start-Stop Control Register on page 13-27
TRCSEQEVR0 RW Sequencer State Transition Control Registers 0-2 on page 13-27
TRCSEQEVR1 RW Sequencer State Transition Control Registers 0-2 on page 13-27
TRCSEQEVR2 RW Sequencer State Transition Control Registers 0-2 on page 13-27
TRCSEQRSTEVR RW Sequencer Reset Control Register on page 13-28