ARM Cortex-A53 MPCore - Compliance

Introduction
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 1-3
ID021414 Non-Confidential
1.2 Compliance
The Cortex-A53 processor complies with, or implements, the specifications described in:
• ARM architecture.
• Interconnect architecture.
• Generic Interrupt Controller architecture on page 1-4.
• Generic Timer architecture on page 1-4.
• Debug architecture on page 1-4.
• Embedded Trace Macrocell architecture on page 1-4.
This TRM complements architecture reference manuals, architecture specifications, protocol
specifications, and relevant external standards. It does not duplicate information from these
sources.
1.2.1 ARM architecture
The Cortex-A53 processor implements the ARMv8-A architecture. This includes:
• Support for both AArch32 and AArch64 Execution states.
• Support for all exception levels, EL0, EL1, EL2, and EL3, in each execution state.
• The A32 instruction set, previously called the ARM instruction set.
• The T32 instruction set, previously called the Thumb instruction set.
• The A64 instruction set.
The Cortex-A53 processor supports the following architecture extensions:
• Optional Advanced SIMD and Floating-point Extension for integer and floating-point
vector operations.
Note
— The Advanced SIMD architecture, its associated implementations, and supporting
software, are commonly referred to as NEON technology.
— To perform floating-point operations, you must implement the Advanced SIMD and
Floating-point Extension. There is no software API library for floating-point in the
ARMv8-A architecture.
— You cannot implement floating-point without Advanced SIMD.
• Optional ARMv8 Cryptography Extensions.
Note
You cannot implement the Cryptography Extensions without Advanced SIMD and
Floating-point.
See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for
more information.
1.2.2 Interconnect architecture
The Cortex-A53 bus interface natively supports one of:
• AMBA 4 ACE bus architecture. See the ARM
®
AMBA
®
AXI and ACE Protocol
Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite.
• AMBA 5 CHI bus architecture. See the ARM
®
AMBA
®
5 CHI Protocol Specification.