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ARM Cortex-A53 MPCore - Appendix B Cortex-A53 Processor Aarch32 Unpredictable Behaviors; Appendix C Revisions

ARM Cortex-A53 MPCore
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ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. C-1
ID021414 Non-Confidential
Appendix C
Revisions
This appendix describes the technical changes between released issues of this book.
Table C-1 Issue A
Change Location Affects
First release - -
Table C-2 Differences between Issue A and Issue B
Change Location Affects
Cluster device shutdown sequence updated Cluster shutdown mode without system driven L2 flush on
page 2-22
All revisions
Revision information updated. Chapter 4 System Control r0p1
GIC programmers model on page 9-3
ETM register descriptions on page 13-13
Peripheral Identification Register 2 on page 11-29
Peripheral Identification Register 2 on page 12-29
Peripheral Identification Register 2 on page 14-12
Peripheral Identification Register 2 on page 11-47
ID_AA64MMFR0_EL1 description updated
AArch64 Memory Model Feature Register 0, EL1 on page 4-41 All revisions

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