Cortex-A53 Processor AArch32 unpredictable Behaviors
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. B-11
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B.5 Other UNPREDICTABLE behaviors
This section describes other UNPREDICTABLE behaviors:
• CSSELR indicates a cache that is not implemented
• HDCR.HPMN is set to 0, or to a value larger than PMCR.N
B.5.1 CSSELR indicates a cache that is not implemented
If CSSELR indicates a cache that is not implemented, then on a read of the CCSIDR the
behavior is
CONSTRAINED UNPREDICTABLE, and can be one of the following:
• The CCSIDR read is treated as
NOP
.
• The CCSIDR read is
UNDEFINED.
• The CCSIDR read returns an
UNKNOWN value (preferred).
B.5.2 HDCR.HPMN is set to 0, or to a value larger than PMCR.N
If HDCR.HPMN is set to 0, or to a value larger than PMCR.N, then the behavior in Non-secure
EL0 and EL1 is
CONSTRAINED UNPREDICTABLE, and one of the following must happen:
• The number of counters accessible is an
UNKNOWN non-zero value less than PMCR.N.
• There is no access to any counters.
For reads of HDCR.HPMN by EL2 or higher, if this field is set to 0 or to a value larger than
PMCR.N, the processor must return a
CONSTRAINED UNPREDICTABLE value that is one of:
• PMCR.N.
• The value that was written to HDCR.HPMN.
• (The value that was written to HDCR.HPMN) modulo 2h, where h is the smallest number
of bits required for a value in the range 0 to PMCR.N.
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