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ARM Cortex-A53 MPCore - Generic Timer Signals

ARM Cortex-A53 MPCore
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Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-8
ID021414 Non-Confidential
A.6 Generic Timer signals
Table A-5 shows the Generic Timer signals.
Table A-5 Generic Timer signals
Signal Direction Description
nCNTHPIRQ[CN:0] Output Hypervisor physical timer event.
nCNTPNSIRQ[CN:0] Output Non-secure physical timer event.
nCNTPSIRQ[CN:0] Output Secure physical timer event.
nCNTVIRQ[CN:0] Output Virtual physical timer event.
CNTCLKEN Input Counter clock enable.
This clock enable must be inserted one cycle before the CNTVALUEB bus.
CNTVALUEB[63:0] Input Global system counter value in binary format.

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