Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-7
ID021414 Non-Confidential
GICCDISABLE Input Globally disables the CPU interface logic and routes the “External” signals directly to the
processor:
0
Enable the GIC CPU interface logic.
1
Disable the GIC CPU interface logic.
Required to enable use of non-ARM interrupt controllers.
ICDTVALID Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TVALID
indicates that the master is driving a valid transfer.
ICDTREADY Output AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TREADY
indicates that the slave can accept a transfer in the current cycle.
ICDTDATA[15:0] Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TDATA is the
primary payload that is used to provide the data that is passing across the interface.
ICDTLAST Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TLAST
indicates the boundary of a packet.
ICDTDEST[1:0] Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TDEST
provides routing information for the data stream.
ICCTVALID Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TVALID
indicates that the master is driving a valid transfer.
ICCTREADY Input AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TREADY
indicates that the slave can accept a transfer in the current cycle.
ICCTDATA[15:0] Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TDATA is the
primary payload that is used to provide the data that is passing across the interface
ICCTLAST Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TLAST
indicates the boundary of a packet.
ICCTID[1:0] Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor. TID is the data stream
identifier that indicates different streams of data.
Table A-4 GIC signals (continued)
Signal Direction Description
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