Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-13
ID021414 Non-Confidential
13.8 ETM register descriptions
This section describes the implementation-specific ETM trace unit registers in the Cortex-A53
processor. Table 13-3 on page 13-10 provides cross-references to individual registers.
The ARM
®
ETM
™
Architecture Specification, ETMv4 describes the other ETM trace unit
registers.
13.8.1 Programming Control Register
The TRCPRGCTLR characteristics are:
Purpose Enables the ETM trace unit.
Usage constraints See Controlling ETM trace unit programming on page 13-8.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-3 shows the TRCPRGCTLR bit assignments.
Figure 13-3 TRCPRGCTLR bit assignments
Table 13-4 shows the TRCPRGCTLR bit assignments.
The TRCPRGCTLR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x004
.
13.8.2 Status Register
The TRCSTATR characteristics are:
Purpose Indicates the ETM trace unit status.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-4 on page 13-14 shows the TRCSTATR bit assignments.
Table 13-4 TRCPRGCTLR bit assignments
Bits Name Function
[31:1] - Reserved,
RES0.
[0] EN Trace program enable:
0
The ETM trace unit interface in the processor is disabled, and clocks are enabled only when
necessary to process APB accesses, or drain any already generated trace. This is the reset value.
1
The ETM trace unit interface in the processor is enabled, and clocks are enabled. Writes to most
trace registers are ignored
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