ARM Cortex-A53 MPCore - Memory-Mapped Register Summary

Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-23
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12.7 Memory-mapped register summary
Table 12-15 shows the PMU registers that are accessible through the internal memory-mapped
interface and the external debug interface. For those registers not described in this chapter, see
the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
Table 12-15 Memory-mapped PMU register summary
Offset Name Type Description
0x000 PMEVCNTR0_EL0 RW Performance Monitor Event Count Register 0
0x004 --Reserved
0x008 PMEVCNTR1_EL0 RW Performance Monitor Event Count Register 1
0x00C --Reserved
0x010 PMEVCNTR2_EL0 RW Performance Monitor Event Count Register 2
0x014 --Reserved
0x018 PMEVCNTR3_EL0 RW Performance Monitor Event Count Register 3
0x01C --Reserved
0x020 PMEVCNTR4_EL0 RW Performance Monitor Event Count Register 4
0x024 --Reserved
0x028 PMEVCNTR5_EL0 RW Performance Monitor Event Count Register 5
0x02C-0xF4 --Reserved
0x0F8 PMCCNTR_EL0[31:0] RW Performance Monitor Cycle Count Register
0x0FC PMCCNTR_EL0[63:32] RW
0x100-0x3FC - Reserved
0x400 PMEVTYPER0_EL0 RW Performance Monitor Event Type Register
0x404 PMEVTYPER1_EL0 RW
0x408 PMEVTYPER2_EL0 RW
0x40C PMEVTYPER3_EL0 RW
0x410 PMEVTYPER4_EL0 RW
0x414 PMEVTYPER5_EL0 RW
0x418-0x478 --Reserved
0x47C PMCCFILTR_EL0 RW Performance Monitor Cycle Count Filter Register
0x480-0xBFC --Reserved
0xC00 PMCNTENSET_EL0 RW Performance Monitor Count Enable Set Register
0xC04-0xC1C --Reserved
0xC20 PMCNTENCLR_EL0 RW Performance Monitor Count Enable Clear Register
0xC24-0xC3C --Reserved
0xC40 PMINTENSET_EL1 RW Performance Monitor Interrupt Enable Set Register