ARM Cortex-A53 MPCore - Page 478

Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-24
ID021414 Non-Confidential
0xC44-0xC5C --Reserved
0xC60 PMINTENCLR_EL1 RW Performance Monitor Interrupt Enable Clear Register
0xC64-0xC7C --Reserved
0xC80 PMOVSCLR_EL0 RW Performance Monitor Overflow Flag Status Register
0xC84-0xC9C --Reserved
0xCA0 PMSWINC_EL0 WO Performance Monitor Software Increment Register
0xCA4-0xCBC --Reserved
0xCC0 PMOVSSET_EL0 RW Performance Monitor Overflow Flag Status Set Register
0xCC4-0xDFC --Reserved
0xE00 PMCFGR RO Performance Monitor Configuration Register on page 12-26
0xE04
PMCR_EL0
a
RW Performance Monitors Control Register
0xE08-0xE1C --Reserved
0xE20 PMCEID0_EL0 RO Performance Monitors Common Event Identification Register 0 on page 12-9
0xE24 PMCEID1_EL0 RO Performance Monitor Common Event Identification Register 1
0xE28 - 0xFA4 --Reserved
0xFA8 PMDEVAFF0 RO Performance Monitors Device Affinity Register 0, see Multiprocessor Affinity
Register on page 4-15
0xFAC PMDEVAFF1 RO Performance Monitors Device Affinity Register 1, RES0
0xFB0 PMLAR WO Performance Monitor Lock Access Register
0xFB4 PMLSR RO Performance Monitor Lock Status Register
0xFB8 PMAUTHSTATUS RO Performance Monitor Authentication Status Register
0xFBC PMDEVARCH Performance Monitor Device Architecture Register
0xFC0-0xFC8 --Reserved
0xFCC PMDEVTYPE RO Performance Monitor Device Type Register
0xFD0 PMPIDR4 RO Peripheral Identification Register 4 on page 12-30
0xFD4 PMPIDR5 RO Peripheral Identification Register 5-7 on page 12-31
0xFD8 PMPIDR6 RO
0xFDC PMPIDR7 RO
0xFE0 PMPIDR0 RO Peripheral Identification Register 0 on page 12-27
0xFE4 PMPIDR1 RO Peripheral Identification Register 1 on page 12-28
0xFE8 PMPIDR2 RO Peripheral Identification Register 2 on page 12-29
0xFEC PMPIDR3 RO Peripheral Identification Register 3 on page 12-30
0xFF0 PMCIDR0 RO Component Identification Register 0 on page 12-32
Table 12-15 Memory-mapped PMU register summary (continued)
Offset Name Type Description