ARM Cortex-A53 MPCore - 11.10 External Debug Interface

Debug
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11.10 External debug interface
The system can access memory-mapped debug registers through the APB interface. The APB
interface is compliant with the AMBA 4 APB interface.
Figure 11-20 shows the debug interface implemented in the Cortex-A53 processor. For more
information on these signals, see the ARM
®
CoreSight
™
Architecture Specification.
Figure 11-20 External debug interface, including APBv3 slave port
This section describes external debug interface in:
• Debug memory map.
• DBGPWRDUP debug signal on page 11-39.
• DBGL1RSTDISABLE debug signal on page 11-39.
• Changing the authentication signals on page 11-40.
11.10.1 Debug memory map
The basic memory map supports up to four cores in the cluster. Table 11-26 shows the address
mapping for the Cortex-A53 processor debug APB components when configured for v8 Debug
memory map.
Each component in the table requires 4KB, and uses the bottom 4KB of each 64KB region. The
remaining 60KB of each region is reserved.
DBGEN
SPIDEN
NIDEN
SPNIDEN
Authentication
interface
COMMTX
COMMRX
DCC
handshake
DBGACK
EDBGRQ
DBGPWRDUP
Power
controller
interface
PSELDBG
PADDRDBG
PRDATADBG
PWDATADBG
PENABLEDBG
PREADYDBG
PSLVERRDBG
PWRITEDBG
PCLKENDBG
Debug slave
port, APBv3
Debug state
entry
DBGROMADDR
DBGROMADDRV
Processor
DBGRSTREQ
Reset
controller
interface
DBGPWRUPREQ
nCOMMIRQ
DBGNOPWRDWN
nPRESETDBG
Configuration
PADDRDBG31
Table 11-26 Address mapping for APB components
Address offset [21:0]
Component
a
0x000000 - 0x000FFF Cortex-A53 APB ROM table
0x010000 - 0x010FFF CPU 0 Debug
0x020000 - 0x020FFF CPU 0 CTI