Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-3
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13.2 ETM trace unit generation options and resources
Table 13-1 shows the trace generation options implemented in the Cortex-A53 ETM trace unit.
Table 13-1 ETM trace unit generation options implemented
Description Configuration
Instruction address size in bytes 8
Data address size in bytes 0
Data value size in bytes 0
Virtual Machine ID size in bytes 1
Context ID size in bytes 4
Support for conditional instruction tracing Not implemented
Support for tracing of data Not implemented
Support for tracing of load and store instructions as P0 elements Not implemented
Support for cycle counting in the instruction trace Implemented
Support for branch broadcast tracing Implemented
Exception Levels implemented in Non-secure state EL2, EL1, EL0
Exception Levels implemented in Secure state EL3, EL1, EL0
Number of events supported in the trace 4
Return stack support Implemented
Tracing of SError exception support Implemented
Instruction trace cycle counting minimum threshold 1
Size of Trace ID 7 bits
Synchronization period support Read-write
Global timestamp size 64 bits
Number of cores available for tracing 1
ATB trigger support Implemented
Low power behavior override Implemented
Stall control support Implemented
Support for no overflows in the trace Not implemented
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