Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-6
ID021414 Non-Confidential
A.5 Generic Interrupt Controller signals
Table A-4 shows the Generic Interrupt Controller (GIC) signals.
Table A-4 GIC signals
Signal Direction Description
nFIQ[CN:0] Input FIQ request. Active-LOW, level sensitive, asynchronous FIQ interrupt request:
0
Activate FIQ interrupt.
1
Do not activate FIQ interrupt.
The processor treats the nFIQ input as level-sensitive. The nFIQ input must be asserted
until the processor acknowledges the interrupt.
nIRQ[CN:0] Input IRQ request input lines. Active-LOW, level sensitive, asynchronous interrupt request:
0
Activate interrupt.
1
Do not activate interrupt.
The processor treats the nIRQ input as level-sensitive. The nIRQ input must be asserted
until the processor acknowledges the interrupt.
nSEI[CN:0] Input System Error Interrupt request. Active-LOW, edge sensitive:
0
Activate SEI request.
1
Do not activate SEI request.
nVFIQ[CN:0] Input Virtual FIQ request. Active-LOW, level sensitive, asynchronous FIQ interrupt request:
0
Activate FIQ interrupt.
1
Do not activate FIQ interrupt.
The processor treats the nVFIQ input as level-sensitive. The nVFIQ input must be
asserted until the processor acknowledges the interrupt. If the GIC is enabled by tying the
GICCDISABLE input pin LOW, the nVFIQ input pin must be tied off to HIGH. If the
GIC is disabled by tying the GICCDISABLE input pin HIGH, the nVFIQ input pin can
be driven by an external GIC in the SoC.
nVIRQ[CN:0] Input Virtual IRQ request. Active-LOW, level sensitive, asynchronous interrupt request:
0
Activate interrupt.
1
Do not activate interrupt.
The processor treats the nVIRQ input as level-sensitive. The nVIRQ input must be
asserted until the processor acknowledges the interrupt. If the GIC is enabled by tying the
GICCDISABLE input pin LOW, the nVIRQ input pin must be tied off to HIGH. If the
GIC is disabled by tying the GICCDISABLE input pin HIGH, the nVIRQ input pin can
be driven by an external GIC in the SoC.
nVSEI[CN:0] Input Virtual System Error Interrupt request. Active-LOW, edge sensitive:
0
Activate virtual SEI request.
1
Do not activate virtual SEI request.
nREI[CN:0] Input RAM Error Interrupt request. Active-LOW, edge sensitive:
0
Activate REI request. Reports an asynchronous RAM error in the system.
1
Do not activate REI request.
nVCPUMNTIRQ[CN:0] Output Virtual CPU interface maintenance interrupt PPI output.
PERIPHBASE[39:18] Input Specifies the base address for the GIC registers. This value is sampled into the CP15
Configuration Base Address Register (CBAR) at reset.
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