ARM Cortex-A53 MPCore - DFT and MBIST Interface Signals

Signal Descriptions
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A.18 DFT and MBIST interface signals
This section describes:
• DFT interface.
• MBIST interface.
A.18.1 DFT interface
Table A-40 shows the DFT interface signals.
A.18.2 MBIST interface
Table A-41 shows the MBIST interface signals.
Note
A Cortex-A53 processor does not include an external MBIST address and data interface port.
The MBIST address and data interface ports are internally tied-off in the design, and you can
insert MBIST into the design before synthesis. The process of adding MBIST into the design
can be done automatically by an EDA MBIST tool.
Table A-40 DFT interface signals
Signal Direction Description
DFTRAMHOLD Input Disable the RAM chip select during scan testing
DFTRSTDISABLE Input Disable internal synchronized reset during scan shift
DFTSE Input Scan shift enable, forces on the clock grids during scan shift
DFTMCPHOLD Input Disable Multicycle Paths on RAM interfaces
Table A-41 MBIST interface signals
Signal Direction Description
MBISTREQ Input MBIST test request
nMBISTRESET Input MBIST reset