ARM Cortex-A53 MPCore - Additional Memory Attributes

Level 2 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-17
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7.5 Additional memory attributes
The Cortex-A53 processor simplifies the coherency logic by downgrading some memory types:
• Memory that is marked as both Inner Write-Back Cacheable and Outer Write-Back
Cacheable is cached in the L1 Data cache and the L2 cache.
• Memory that is marked Inner Write-Through is downgraded to Non-cacheable.
• Memory that is marked Outer Write-Through or Outer Non-cacheable is downgraded to
Non-cacheable, even if the inner attributes are Write-Back cacheable.
The attributes provided on ARCACHE or AWCACHE in ACE configurations or MemAttr and
SnpAttr in CHI configurations are these downgraded attributes, and indicate how the
interconnect must treat the transaction.
Some interconnects or bus protocols might require more information about the memory type
and, for these cases, the cluster exports the unaltered memory attribute information from the
translation tables stored in the TLB. These signals are for information only, and do not form part
of the ACE or CHI protocols.
In an ACE configuration there is a RDMEMATTR bus for the read channel and a
WRMEMATTR bus for the write channel.
In a CHI configuration there is single REQMEMATTR bus.
Table 7-15 describes the encodings on the memory attribute bus.
Table 7-15 Memory attribute bus encodings
Bits Encoding
[7] Outer shareable.
Always set for device memory or memory that is both inner and outer non-cacheable.
[6:3] Outer memory type, or device type.
If bits[1:0] indicate Device, then:
0000 nGnRnE.
0100 nGnRE.
1000 nGRE.
1100 GRE.
If bits[1:0] indicate Normal, then:
0100 NC.
10RW WT.
11RW WB.
Where R is read allocate hint, W is write allocate hint.
[2] Inner shareable.
Anything with bit[7] set must also have bit[2] set.
[1:0] Inner memory type:
00 Device.
01 NC.
10 WT.
11 WB.