Level 2 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-16
ID021414 Non-Confidential
7.4.4 CHI transaction IDs
Table 7-14 shows the CHI transaction IDs used for each type of transaction.
7.4.5 CHI nodes
CHI transactions are sent to a specific node in the interconnect based on the:
• Type of access.
• Address of the access.
• Settings of the System Address Map.
Addresses that map to an HN-F node can be marked as cacheable memory in the page tables,
and can take part in the cache coherency protocol. Addresses that map to an HN-I or MN must
be marked as device or non-cacheable memory.
Table 7-14 CHI transactions
Transaction ID Description
000nnxxx Transaction from core nn. Can be a:
• Read transaction.
• Write transaction.
• Cache maintenance transaction.
• DVM transaction.
• Barrier transaction.
001001xx Transaction from the ACP interface. Can be a read or write.
00101110 Barrier generated in response to a DVM sync snoop from the interconnect.
0100xxxx Eviction from L1 or L2 cache. The number of IDs used depends on the configuration.
To Next Page
Loading...
