Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-17
ID021414 Non-Confidential
11.6 AArch32 debug register descriptions
This section describes the debug registers in the AArch32 Execution state. The AArch32 debug
register summary on page 11-15 provides cross-references to the individual registers.
11.6.1 Debug ID Register
The DBGDIDR characteristics are:
Purpose Specifies:
• The version of the Debug architecture that is implemented.
• Some features of the debug implementation.
Usage constraints This register is accessible as follows:
Configurations There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes See the register summary in Table 11-7 on page 11-15.
Figure 11-5 shows the DBGDIDR bit assignments.
Figure 11-5 DBGDIDR bit assignments
Table 11-8 shows the DBGDIDR bit assignments.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
RO RO RO RO RO RO RO
31 28 27 24 23 20 19 16 15 14 13 12 11 0
WRPs BRPs CTX_CMPs Version
RES
0
DEVID_imp
PCSR_imp
SE
nSUHD_imp
Table 11-8 DBGDIDR bit assignments
Bits Name Function
[31:28] WRPs The number of Watchpoint Register Pairs (WRPs) implemented. The number of implemented WRPs is one
more than the value of this field. The value is:
0x3
The processor implements 4 WRPs.
This field has the same value as ID_AA64DFR0_EL1.WRPs.
[27:24] BRPs The number of Breakpoint Register Pairs (BRPs) implemented. The number of implemented BRPs is one
more than the value of this field. The value is:
0x5
The processor implements 6 BRPs.
This field has the same value as ID_AA64DFR0_EL1.BRPs.
[23:20] CTX_CMPs The number of BRPs that can be used for Context matching. This is one more than the value of this field.
The value is:
0x1
The processor implements two Context matching breakpoints, breakpoints 4 and 5.
This field has the same value as ID_AA64DFR0_EL1.CTX_CMPs.
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