Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-16
ID021414 Non-Confidential
0x458
c0 5 c5 0 DBGBCR5 RW Debug Breakpoint Control Registers, EL1 on
page 11-8
0x800
c0 6 c0 0 DBGWVR0 RW Debug Watchpoint Value Register 0
0x810
c0 6 c1 0 DBGWVR1 RW Debug Watchpoint Value Register 1
0x820
c0 6 c2 0 DBGWVR2 RW Debug Watchpoint Value Register 2
0x830
c0 6 c3 0 DBGWVR3 RW Debug Watchpoint Value Register 3
0x808
c0 7 c0 0 DBGWCR0 RW Debug Watchpoint Control Registers, EL1 on
page 11-11
0x818
c0 7 c1 0 DBGWCR1 RW Debug Watchpoint Control Registers, EL1 on
page 11-11
0x828
c0 7 c2 0 DBGWCR2 RW Debug Watchpoint Control Registers, EL1 on
page 11-11
0x838
c0 7 c3 0 DBGWCR3 RW Debug Watchpoint Control Registers, EL1 on
page 11-11
- c1 0 c0 0 DBGDRAR[31:0] RO
Debug ROM Address Register
- - - c1 - DBGDRAR[63:0] RO
0x444
c1 1 c4 0 DBGBXVR4 RW Debug Breakpoint Extended Value Register 4
0x454
c1 1 c5 0 DBGBXVR5 RW Debug Breakpoint Extended Value Register 5
0x300
c1 4 c0 0 DBGOSLAR WO Debug OS Lock Access Register
- c1 4 c1 0 DBGOSLSR RO Debug OS Lock Status Register
- c1 4 c3 0 DBGOSDLR RW Debug OS Double Lock Register
0x310
c1 4 c4 0 DBGPRCR RW Debug Power/Reset Control Register
-c22c00
DBGDSAR[31:0]
b
RO Debug Self Address Register RES0
--0c2-
DBGDSAR[63:0]
b
RO
- c7 7 c0 0 DBGDEVID2 RO Debug Device ID Register 2,
RES0
- c7 7 c1 0 DBGDEVID1 RO Debug Device ID Register 1 on page 11-19
- c7 7 c2 0 DBGDEVID RO Debug Device ID Register on page 11-18
0xFA0
c7 6 c8 0 DBGCLAIMSET RW Debug Claim Tag Set Register
0xFA4
c7 6 c9 0 DBGCLAIMCLR RW Debug Claim Tag Clear Register
0xFB8
c7 6 c14 0 DBGAUTHSTATUS RO Debug Authentication Status Register
a. Previously returned information about the address of the instruction that accessed a watchpoint address. This register is now deprecated and
is
RES0.
b. Previously defined the offset from the base address defined in DBGDRAR of the physical base address of the debug registers for the
processor. This register is now deprecated and
RES0.
Table 11-7 AArch32 debug register summary (continued)
Offset CRn Op2 CRm Op1 Name Type Description
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