Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-18
ID021414 Non-Confidential
Table 2-5 describes the supported power domain states for individual cores. The power domain
state in each core is independent of all other cores.
You must follow the dynamic power management and powerup and powerdown sequences
described in the following sections. Any deviation from these sequences can lead to
UNPREDICTABLE results.
The supported power modes are:
• Normal state.
• Standby state on page 2-19.
• Individual core shutdown mode on page 2-21.
• Cluster shutdown mode without system driven L2 flush on page 2-22.
• Cluster shutdown mode with system driven L2 flush on page 2-23.
• Dormant mode on page 2-24.
• Retention state on page 2-25.
Normal state
This is the normal mode of operation where all of the processor functionality is available. The
Cortex-A53 processor uses gated clocks and gates to disable inputs to unused functional blocks.
Only the logic in use to perform an operation consumes any dynamic power.
Table 2-4 Supported processor power states
Power domains
Description
PDCORTEXA53 PDL2 PDCPU<n>
Off Off Off Cluster off - L2 RAMs and all cores are off.
Off On/Ret Off L2 Dormant mode - L2 RAMs retained and all cores are off.
On Ret
Off/Ret
a
L2 Retention - L2 RAMs retained and all cores either retained or turned off.
On On See Table 2-5 Cluster L2 RAM active - L2 RAM active and all cores are in either on, off or
retention state.
a. All cores in the cluster to be in WFE, WFI, retention or powered off.
Table 2-5 Supported core power states
Power domains
Description
PDCPU PDADVSIMD
Off Off Core off.
On On Core on - Advanced SIMD and Floating-point on.
On Ret AdvSIMD retention - Advanced SIMD and Floating-point in retention.
Ret Ret Core retention - core logic and Advanced SIMD and Floating-point in retention.
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