ARM Cortex-A53 MPCore - Page 40

Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-17
ID021414 Non-Confidential
Figure 2-8 Power domains
2.4.2 Power modes
The power domains can be controlled independently to give different combinations of
powered-up and powered-down domains. However, only some powered-up and powered-down
domain combinations are valid and supported.
Table 2-4 on page 2-18 and Table 2-5 on page 2-18 show the supported power domain states for
the Cortex-A53 processor. The terms used are defined in Table 2-3.
Caution
States not shown in Table 2-4 on page 2-18 and Table 2-5 on page 2-18 are unsupported and
must not occur.
System
PDSOC
Cortex-A53 processor
PDCORTEXA53
L2
PDL2*
Core <n>
PDCPU<n>
Core <n>
excluding RAM
APB
Master
Interface
Data
cache
RAM
ATB
Instruction
cache
RAM
TLB RAM
*If implementation includes Dormant mode support
Advanced SIMD
and Floating-point
L2 excluding RAM
L1
Duplicate
tag RAM
0
L1
Duplicate
tag RAM
1
L1
Duplicate
tag RAM
2
L1
Duplicate
tag RAM
3
L2 cache
RAM
PDADVSIMD<n>
Debug
domain
registers
Table 2-3 Power state description
Power state Description
Off Block is power gated
Ret Logic or RAM retention power only
On Block is active