Generic Interrupt Controller CPU Interface
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 9-3
ID021414 Non-Confidential
9.2 GIC programmers model
This section describes the programmers model for the GIC CPU interface in:
• CPU interface register summary.
• CPU interface register descriptions on page 9-4.
• Virtual interface control register summary on page 9-5.
• Virtual interface control register descriptions on page 9-6.
• Virtual CPU interface register summary on page 9-7.
• Virtual CPU interface register descriptions on page 9-8.
9.2.1 Memory map
The Cortex-A53 GIC CPU Interface implements a memory-mapped interface. The
memory-mapped interface is offset from PERIPHBASE. Table 9-1 lists the address ranges.
These registers are not available if GICCDISABLE is asserted.
9.2.2 CPU interface register summary
Each CPU interface block provides the interface for a Cortex-A53 processor that interfaces with
a GIC distributor within the system. Each CPU interface provides a programming interface for:
• Enabling the signaling of interrupt requests by the CPU interface.
• Acknowledging an interrupt.
• Indicating completion of the processing of an interrupt.
• Setting an interrupt priority mask for the processor.
• Defining the preemption policy for the processor.
• Determining the highest priority pending interrupt for the processor.
• Generating SGIs.
For more information on the CPU interface, see the ARM Generic Interrupt Controller
Architecture Specification.
Table 9-2 on page 9-4 lists the registers for the CPU interface.
Table 9-1 Memory Map
Address range Functional block
0x00000-0x01FFF CPU Interface
0x02000-0x0FFFF Reserved
0x10000-0x10FFF Virtual Interface Control
0x11000-0x1FFFF Reserved
0x20000-0x21FFF Virtual CPU Interface
0x22000-0x2EFFF Reserved
0x2F000-0x30FFF Alias of Virtual CPU Interface
0x31FFF-0x3FFFF Reserved
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