ARM Cortex-A53 MPCore - Page 393

Generic Interrupt Controller CPU Interface
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All the registers in Table 9-2 are word-accessible. Registers not described in this table are RES0.
See the ARM
®
Generic Interrupt Controller Architecture Specification for more information.
9.2.3 CPU interface register descriptions
This section describes only registers whose implementation is specific to the Cortex-A53
processor. All other registers are described in the ARM
®
Generic Interrupt Controller
Architecture Specification Table 9-2 provides cross-references to individual registers.
Active Priority Register
The GICC_APR0 characteristics are:
Purpose Provides support for preserving and restoring state in power management
applications.
Usage constraints This register is banked to provide Secure and Non-secure copies. This
ensures that Non-secure accesses do not interfere with Secure operation.
Configurations Available in all configurations.
Attributes See the register summary in Table 9-2.
The Cortex-A53 processor implements the GICC_APR0 according to the recommendations
described in the ARM
®
Generic Interrupt Controller Architecture Specification.
Table 9-2 CPU interface register summary
Name Type Reset Description
GICC_CTLR RW
0x00000000 CPU Interface Control Register
GICC_PMR RW
0x00000000 Interrupt Priority Mask Register
GICC_BPR RW
0x00000002 (S)
a
0x00000003 (NS)
b
a. S = Secure.
b. NS = Non-secure.
Binary Point Register
GICC_IAR RO - Interrupt Acknowledge Register
GICC_EOIR WO - End Of Interrupt Register
GICC_RPR RO 0x000000FF Running Priority Register
GICC_HPPIR RO
0x000003FF Highest Priority Pending Interrupt Register
GICC_ABPR RW
0x00000003 Aliased Binary Point Register
GICC_AIAR RO
- Aliased Interrupt Acknowledge Register
GICC_AEOIR WO
- Aliased End of Interrupt Register
GICC_AHPPIR RO
0x000003FF Aliased Highest Priority Pending Interrupt Register
GICC_APR0 RW
0x00000000 Active Priority Register
GICC_NSAPR0 RW
0x00000000 Non-secure Active Priority Register
GICC_IIDR RO
0x0034243B CPU Interface Identification Register on page 9-5
GICC_DIR WO - Deactivate Interrupt Register