ARM Cortex-A53 MPCore - Aarch32 PMU Register Descriptions

Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-16
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12.6 AArch32 PMU register descriptions
This section describes the Cortex-A53 processor PMU registers in the AArch32 Execution state.
Table 12-9 on page 12-14 provides cross-references to individual registers.
12.6.1 Performance Monitors Control Register
The PMCR characteristics are:
Purpose Provides details of the Performance Monitors implementation, including
the number of counters implemented, and configures and controls the
counters.
Usage constraints This register is accessible as follows:
This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.
Configurations The PMCR is architecturally mapped to:
• The AArch64 PMCR_EL0 register. See Performance Monitors
Control Register on page 12-7.
• The external PMCR_EL0 register.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes PMCR is a 32-bit register.
Figure 12-5 shows the PMCR bit assignments.
Figure 12-5 PMCR bit assignments
Table 12-10 shows the PMCR bit assignments.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config Config RW RW RW RW RW
E
31 24 23 16 15 11 10 6 5 4 3 2 1 0
IMP IDCODE N RES0DPXDCPLC
7
Table 12-10 PMCR bit assignments
Bits Name Function
[31:24] IMP Implementer code:
0x41 ARM.
This is a read-only field.
[23:16] IDCODE Identification code:
0x03 Cortex-A53.
This is a read-only field.
[15:11] N Number of event counters.
0b00110 Six counters.
[10:7] - Reserved,
RES0.