ARM Cortex-A53 MPCore - Interfaces

Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-7
ID021414 Non-Confidential
2.2 Interfaces
The Cortex-A53 processor has the following external interfaces:
• Master memory interface.
• Accelerator Coherency Port.
• External debug interface.
• Trace interface.
• CTI on page 2-8.
• DFT on page 2-8.
• MBIST on page 2-8.
• Q-channel on page 2-8.
2.2.1 Master memory interface
The processor implements the AMBA 4 ACE or AMBA 5 CHI interface:
• ACE is an extension to the AXI protocol and provides the following enhancements:
— Support for hardware cache coherency.
— Barrier transactions that guarantee transaction ordering.
— Distributed virtual memory messaging, enabling management of a virtual memory
system across multiple MPCore clusters.
See the ARM
®
AMBA
®
AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite,
ACE and ACE-Lite for more information.
• CHI is a protocol that provides an architecture for connecting multiple nodes using a
scalable interconnect. The nodes on the interconnect might be cores, clusters, I/O bridges,
memory controllers, or graphics processors.
See the ARM
®
AMBA
®
5 CHI Protocol Specification.
2.2.2 Accelerator Coherency Port
The processor supports an Accelerator Coherency Port (ACP). This is an AMBA 4 AXI slave
interface. The ACP is provided to reduce software cache maintenance operations when sharing
memory regions with other masters, and to allow other masters to allocate data into the L2
cache.
The ACP slave interface can receive coherent requests from an external master, but it cannot
propagate coherent requests from the Cortex-A53 processor.
See ACP on page 7-19 and the ARM
®
AMBA
®
AXI and ACE Protocol Specification AXI3, AXI4,
and AXI4-Lite, ACE and ACE-Lite for more information.
2.2.3 External debug interface
The processor supports an AMBA 3 APB slave interface that enables access to the debug
registers. See the ARM
®
CoreSight
™
Architecture Specification for more information.
2.2.4 Trace interface
The processor supports dedicated AMBA 4 ATB interfaces for each core that outputs trace
information for debugging. The ATB interface is compatible with the CoreSight architecture.
See the ARM
®
AMBA
®
4 ATB Protocol Specification for more information.