Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-8
ID021414 Non-Confidential
2.2.5 CTI
The Cortex-A53 processor implements a single cross trigger channel interface. This external
interface is connected to the CoreSight Cross Trigger Interface (CTI) corresponding to each
core through a simplified Cross Trigger Matrix (CTM). See Chapter 14 Cross Trigger for more
information.
2.2.6 DFT
The processor implements a Design For Test (DFT) interface that enables an industry standard
Automatic Test Pattern Generation (ATPG) tool to test logic outside of the embedded memories.
See DFT interface on page A-32 for information on these test signals.
2.2.7 MBIST
The Memory Built In Self Test (MBIST) controller interface provides support for manufacturing
test of the memories embedded in the Cortex-A53 processor. See MBIST interface on page A-32
for information on this interface.
2.2.8 Q-channel
The Q-channel interfaces enable communication to an external power controller. See
Communication to the Power Management Controller on page 2-26.
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