ARM Cortex-A53 MPCore - External Debug Interface

Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-25
ID021414 Non-Confidential
A.13 External debug interface
The following sections describe the external debug interface signals:
• APB interface signals.
• Miscellaneous debug signals.
A.13.1 APB interface signals
Table A-34 shows the APB interface signals.
Note
You must balance all APB interface signals with respect to CLKIN and time them relative to
PCLKENDBG.
A.13.2 Miscellaneous debug signals
Table A-35 on page A-26 shows the miscellaneous Debug signals.
Table A-34 APB interface signals
Signal Direction Description
nPRESETDBG Input APB reset, active-LOW:
0 Apply reset to APB interface.
1 Do not apply reset to APB interface.
PADDRDBG[21:2] Input APB address bus.
PADDRDBG31 Input APB address bus bit[31]:
0 Not an external debugger access.
1 External debugger access.
PCLKENDBG Input APB clock enable.
PENABLEDBG Input Indicates the second and subsequent cycles of an APB transfer.
PRDATADBG[31:0] Output APB read data.
PREADYDBG Output APB slave ready.
An APB slave can deassert PREADYDBG to extend a transfer by inserting wait
states.
PSELDBG Input Debug bus access.
PSLVERRDBG Output APB slave transfer error:
0 No transfer error.
1 Transfer error.
PWDATADBG[31:0] Input APB write data.
PWRITEDBG Input APB read or write signal:
0 Reads from APB.
1 Writes to APB.