ARM Cortex-A53 MPCore - Timing Diagrams

Preface
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ix
ID021414 Non-Confidential
Timing diagrams
The figure Key to timing diagram conventions explains the components used in timing
diagrams. Variations, when they occur, have clear labels. You must not assume any timing
information that is not explicit in the diagrams.
Shaded bus and signal areas are
UNDEFINED, so the bus or signal can assume any value within
the shaded area at that time. The actual level is unimportant and does not affect normal
operation.
Key to timing diagram conventions
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Lowercase n At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This section lists publications by ARM and by third parties.
See Infocenter,
http://infocenter.arm.com , for access to ARM documentation.
monospace Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full
command or option name.
monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold Denotes language keywords when used outside example code.
<and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the ARM
®
Glossary.
For example,
IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
Typographical conventions (continued)
Style Purpose
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus