ARM Cortex-A53 MPCore - Reset Signals; A.3 Reset Signals

Signal Descriptions
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A.3 Reset signals
Table A-2 shows the reset and reset control signals.
Note
• See nPRESETDBG in Table A-34 on page A-25.
• See nMBISTRESET in Table A-41 on page A-32.
Table A-2 Reset and reset control signals
Signal Direction Description
nCPUPORESET[CN:0] Input Processor powerup reset:
0 Apply reset to all processor logic
a
.
1 Do not apply reset to all processor logic
a
.
nCORERESET[CN:0] Input Individual core resets excluding Debug and ETM trace unit:
0 Apply reset to processor logic
b
.
1 Do not apply reset to processor logic
b
.
nL2RESET Input L2 memory system reset:
0 Apply reset to shared L2 memory system controller.
1 Do not apply reset to shared L2 memory system controller.
L2RSTDISABLE Input Disable automatic L2 cache invalidate at reset:
0 Hardware resets L2 cache.
1 Hardware does not reset L2 cache.
WARMRSTREQ[CN:0] Output Processor warm reset request
0 Apply warm reset.
1 Do not apply warm reset.
a. Processor logic includes Advanced SIMD and Floating-point, Debug, ETM trace unit, breakpoint and watchpoint logic.
b. Processor logic includes Advanced SIMD and Floating-point, but excludes Debug, ETM trace unit, breakpoint and
watchpoint logic.