The SCU does not support hardware management of coherency of the instruction caches.
Instruction cache linefills perform coherent reads, however, there is no coherency
management of data held in the instruction cache.
• An optional L2 cache that:
— Has a cache RAM size of 128KB, 256KB, 512KB, 1MB, or 2MB.
— Is 16-way set associative.
— Supports 64 byte cache lines.
• A 512-bit wide fetch path from the L2 cache.
• A single 128-bit wide master interface to external memory that:
— Can be implemented using the AMBA 4 ACE or AMBA 5 CHI architectures.
— Supports integer ratios of the processor clock period up to and including 1:1.
— Supports a 40-bit physical address range.
• An optional 128-bit wide I/O coherent ACP interface that can allocate to the L2 cache.
See Chapter 7 Level 2 Memory System for more information.
2.1.8 Cache protection
The Cortex-A53 processor supports cache protection in the form of ECC or parity on all RAM
instances in the processor using two separate implementation options:
• SCU-L2 cache protection.
• CPU cache protection.
These options enable the Cortex-A53 processor to detect and correct a one-bit error in any RAM
and detect two-bit errors in some RAMs.
2.1.9 Debug and trace
The Cortex-A53 processor supports a range of debug and trace features including:
• ARM v8 debug features in each core.
• ETMv4 instruction trace unit for each core.
• CoreSight Cross Trigger Interface (CTI).
• CoreSight Cross Trigger Matrix (CTM).
• Debug ROM.
The Cortex-A53 processor has an Advanced Peripheral Bus version 3 (APBv3) debug interface
that is CoreSight compliant. This permits system access to debug resources, for example, the
setting of watchpoints and breakpoints.
The Cortex-A53 processor provides performance monitors that can be configured to gather
statistics on the operation of each core and the memory system. The performance monitors
implement the ARM PMUv3 architecture.
See Chapter 11 Debug, Chapter 12 Performance Monitor Unit, and Chapter 13 Embedded
Trace Macrocell for more information.
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