Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-5
ID021414 Non-Confidential
The data cache has the following features:
• Pseudo-random cache replacement policy.
• Streaming of sequential data because of multiple word load instructions, for example
LDM
,
LDRD
,
LDP
and
VLDM
.
• Critical word first linefill on a cache miss.
See Chapter 6 Level 1 Memory System for more information.
If the CPU cache protection configuration is implemented, the L1 Data cache tag RAMs and
dirty RAMs are protected by parity bits. The L1 Data cache data RAMs are protected using
Error Correction Codes (ECC). The ECC scheme is Single Error Correct Double Error Detect
(SECDED).
The DCU includes a combined local and global exclusive monitor, used by the Load-Exclusive/
Store-Exclusive instructions. See the ARM
®
Architecture Reference Manual ARMv8, for
ARMv8-A architecture profile for information about these instructions.
Store Buffer
The Store Buffer (STB) holds store operations when they have left the load/store pipeline and
have been committed by the DPU. The STB can request access to the cache RAMs in the DCU,
request the BIU to initiate linefills, or request the BIU to write the data out on the external write
channel. External data writes are through the SCU.
The STB can merge:
• Several store transactions into a single transaction if they are to the same 128-bit aligned
address.
• Multiple writes into an AXI or CHI write burst.
The STB is also used to queue maintenance operations before they are broadcast to other cores
in the cluster.
See Chapter 6 Level 1 Memory System for more information.
Bus Interface Unit and SCU interface
The Bus Interface Unit (BIU) contains the SCU interface and buffers to decouple the interface
from the cache and STB. The BIU interface and the SCU always operate at the processor
frequency.
See Chapter 6 Level 1 Memory System for more information.
2.1.7 L2 memory system
The Cortex-A53 L2 memory system contains the L2 cache pipeline and all logic required to
maintain memory coherence between the cores of the cluster. It has the following features:
• An SCU that connects the cores to the external memory system through the master
memory interface. The SCU maintains data cache coherency between the cores and
arbitrates L2 requests from the cores.
When the Cortex-A53 processor is implemented with a single core, it still includes the
Snoop Control Unit (SCU). See Implementation options on page 1-7 for more
information.
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