Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-4
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• The floating-point architecture includes the floating-point register file and status registers.
It performs floating-point operations on the data held in the floating-point register file.
See the ARM
®
Cortex
®
-A53 MPCore Advanced SIMD and Floating-point Extension Technical
Reference Manual for more information.
2.1.4 Cryptography Extension
The optional Cortex-A53 MPCore Cryptography Extension supports the ARMv8 Cryptography
Extensions. The Cryptography Extension adds new A64, A32, and T32 instructions to
Advanced SIMD that accelerate:
• Advanced Encryption Standard (AES) encryption and decryption.
•The Secure Hash Algorithm (SHA) functions SHA-1, SHA-224, and SHA-256.
• Finite field arithmetic used in algorithms such as Galois/Counter Mode and Elliptic Curve
Cryptography.
See the ARM
®
Cortex
™
-A53 MPCore Processor Cryptography Extension Technical Reference
Manual for more information.
2.1.5 Translation Lookaside Buffer
The Translation Lookaside Buffer (TLB) contains the main TLB and handles all translation
table walk operations for the processor. TLB entries are stored inside a 512-entry, 4-way
set-associative RAM.
If the cache protection configuration is implemented, the TLB RAMs are protected by parity
bits. The parity bits enable any single-bit error to be detected. If an error is detected, the entry
is flushed and fetched again.
See Chapter 6 Level 1 Memory System for more information.
2.1.6 Data side memory system
This section describes the following:
• Data Cache Unit.
• Store Buffer on page 2-5.
• Bus Interface Unit and SCU interface on page 2-5.
Data Cache Unit
The Data Cache Unit (DCU) consists of the following sub-blocks:
•The Level 1 (L1) data cache controller, that generates the control signals for the associated
embedded tag, data, and dirty RAMs, and arbitrates between the different sources
requesting access to the memory resources. The data cache is 4-way set associative and
uses a Physically Indexed Physically Tagged (PIPT) scheme for lookup that enables
unambiguous address management in the system.
• The load/store pipeline that interfaces with the DPU and main TLB.
• The system controller that performs cache and TLB maintenance operations directly on
the data cache and on the instruction cache through an interface with the IFU.
• An interface to receive coherency requests from the Snoop Control Unit (SCU).
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