Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-14
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Figure 13-4 TRCSTATR bit assignments
Table 13-5 shows the TRCSTATR bit assignments.
The TRCSTATR can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x00C
.
13.8.3 Trace Configuration Register
The TRCCONFIGR characteristics are:
Purpose Controls the tracing options.
Usage constraints • This register must always be programmed as part of trace unit
initialization.
• Only accepts writes when the trace unit is disabled.
Configurations Available in all configurations.
Attributes TRCCONFIGR is a 32-bit RW trace register.
See the register summary in Table 13-3 on page 13-10.
Figure 13-5 shows the TRCCONFIGR bit assignments.
Figure 13-5 TRCCONFIGR bit assignments
Table 13-5 TRCSTATR bit assignments
Bits Name Function
[31:2] - Reserved,
RES0.
[1] PMSTABLE Indicates whether the ETM trace unit registers are stable and can be read:
0
The programmers model is not stable.
1
The programmers model is stable.
[0] IDLE Idle status:
0
The ETM trace unit is not idle.
1
The ETM trace unit is idle.
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