Cortex-A53 Processor AArch32 unpredictable Behaviors
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. B-10
ID021414 Non-Confidential
2. In addition, for reserved debug registers in the address ranges
0x400
to
0x4FC
and
0x800
to
0x8FC
, the response is CONSTRAINED UNPREDICTABLE Error or RES0 when the conditions
in 1 do not apply and:
EDAD
AllowExternalDebugAccess()
is FALSE, external debug access is disabled.
3. For reserved Performance Monitor registers in the address ranges
0x000
to
0x0FC
and
0x400
to
0x47C
, the response is CONSTRAINED UNPREDICTABLE Error, or RES0 when the
conditions in 1 and 2 do not apply, and the following errors instead of preferred res0 for
the these registers:
EPMAD
AllowExternalPMUAccess()
is FALSE (external Performance Monitors access is
disabled).
B.4.31 Clearing the clear-after-read EDPRSR bits when Core power domain is on, and
DoubleLockStatus()
is TRUE
The Cortex-A53 processor behaves as indicated in the sole Preference:
• Bits are not cleared to zero.
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