ARM Cortex-A53 MPCore - Page 629

Cortex-A53 Processor AArch32 unpredictable Behaviors
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. B-9
ID021414 Non-Confidential
B.4.23 P = 31: reads and writes of PMXEVCNTR_EL0
The Cortex-A53 processor implements:
•
RES0
B.4.24 n ≥ M: Direct access to PMEVCNTRn_EL0 and PMEVTYPERn_EL0
The Cortex-A53 processor implements:
• If n ≥ N, then the instruction is
UNALLOCATED.
• Otherwise if n ≥ M, then the register is
RES0.
B.4.25 Exiting Debug state while instruction issued through EDITR is in flight
The Cortex-A53 processor implements:
• Option 1: The instruction completes in Debug state before executing the restart.
B.4.26 Using memory-access mode with a non-word-aligned address
The Cortex-A53 processor behaves as indicated in the sole Preference:
• Does unaligned accesses, faulting if these are not permitted for the memory type.
B.4.27 Access to memory-mapped registers mapped to Normal memory
The Cortex-A53 processor behaves as indicated in the sole Preference:
• The access is generated, and accesses might be repeated, gathered, split or resized, in
accordance with the rules for Normal memory, meaning the effect is
UNPREDICTABLE.
B.4.28 Not word-sized accesses or (AArch64 only) doubleword-sized accesses
The Cortex-A53 processor behaves as indicated in the sole Preference:
• Reads occur and return
UNKNOWN data
• Writes set the accessed register(s) to
UNKNOWN.
B.4.29 External debug write to register that is being reset
The Cortex-A53 processor behaves as indicated in the sole Preference:
• Takes reset value
B.4.30 Accessing reserved debug registers
The Cortex-A53 processor deviates from Preferred behavior because the hardware cost to
decode some of these addresses in debug power domain is significantly high:
Actual behavior:
1. For reserved debug and Performance Monitors registers the response is
CONSTRAINED
UNPREDICTABLE Error or RES0, when any of the following error instead of preferred RES0
for reserved debug registers
0x000 - 0xCFC and reserved PMU registers 0x000 - 0xF00 :
Off Core power domain is either completely off, or in a low-power state where the
Core power domain registers cannot be accessed.
DLK
DoubleLockStatus() is TRUE, OS double-lock is locked, that is,
EDPRSR.DLK is 1).
OSLK OSLSR_EL1.OSLK is1, OS lock is locked.