System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-159
ID021414 Non-Confidential
Table 4-150 shows the MPIDR bit assignments.
To access the MPIDR:
MRC p15,0,<Rt>,c0,c0,5 ; Read MPIDR into Rt
Register access is encoded as follows:
The EDDEVAFF0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFA8
.
4.5.3 Revision ID Register
The REVIDR characteristics are:
Purpose Provides implementation-specific minor revision information that can be
interpreted only in conjunction with the Main ID Register.
Usage constraints This register is accessible as follows:
Table 4-150 MPIDR bit assignments
Bits Name Function
[31] M
RES1.
[30] U Indicates a single core system, as distinct from core 0 in a cluster. This value is:
0
Core is part of a cluster.
[29:25] - Reserved,
RES0.
[24] MT Indicates whether the lowest level of affinity consists of logical cores that are implemented using a
multi-threading type approach. This value is:
0
Performance of cores at the lowest affinity level is largely independent.
[23:16] Aff2 Affinity level 2. Second highest level affinity field.
Indicates the value read in the CLUSTERIDAFF2 configuration signal.
[15:8] Aff1 Affinity level 1. Third highest level affinity field.
Indicates the value read in the CLUSTERIDAFF1 configuration signal.
[7:0] Aff0 Affinity level 0. Lowest level affinity field.
Indicates the core number in the Cortex-A53 processor. The possible values are:
0x0
A processor with one core only.
0x0
,
0x1
A cluster with two cores.
0x0
,
0x1
,
0x2
A cluster with three cores.
0x0
,
0x1
,
0x2
,
0x3
A cluster with four cores.
Table 4-151 MPIDR access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0000 101
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
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