System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-160
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Configurations REVIDR is architecturally mapped to AArch64 register REVIDR_EL1.
See Revision ID Register on page 4-16.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes REVIDR is a 32-bit register.
Figure 4-78 shows the REVIDR bit assignments.
Figure 4-78 REVIDR bit assignments
Table 4-152 shows the REVIDR bit assignments.
To access the REVIDR:
MRC p15, 0, <Rt>, c0, c0, 6; Read REVIDR into Rt
Register access is encoded as follows:
4.5.4 TCM Type Register
The processor does not implement the features described by the TCMTR, so this register is
always RAZ.
4.5.5 TLB Type Register
The processor does not implement the features described by the TLBTR, so this register is
always RAZ.
4.5.6 Processor Feature Register 0
The ID_PFR0 characteristics are:
Purpose Gives top-level information about the instruction sets supported by the
processor in AArch32.
Table 4-152 REVIDR bit assignments
Bits Name Function
[31:0] ID number Implementation-specific revision information. The reset value is determined by the specific Cortex-A53
MPCore implementation.
0x00000000
Revision code is zero.
Table 4-153 REVIDR access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0000 110
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