System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-161
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
ID_PFR0 must be interpreted with ID_PFR1.
Configurations ID_PFR0 is architecturally mapped to AArch64 register ID_PFR0_EL1.
See AArch32 Processor Feature Register 0 on page 4-17.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes ID_PFR0 is a 32-bit register.
Figure 4-79 shows the ID_PFR0 bit assignments.
Figure 4-79 ID_PFR0 bit assignments
Table 4-154 shows the ID_PFR0 bit assignments.
To access the ID_PFR0:
MRC p15,0,<Rt>,c0,c1,0 ; Read ID_PFR0 into Rt
Register access is encoded as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Table 4-154 ID_PFR0 bit assignments
Bits Name Function
[31:16] - Reserved,
RES0.
[15:12] State3 Indicates support for Thumb Execution Environment (T32EE) instruction set. This value is:
0x0
Processor does not support the T32EE instruction set.
[11:8] State2 Indicates support for Jazelle. This value is:
0x1
Processor supports trivial implementation of Jazelle.
[7:4] State1 Indicates support for T32 instruction set. This value is:
0x3
Processor supports T32 encoding after the introduction of Thumb-2 technology, and for all 16-bit
and 32-bit T32 basic instructions.
[3:0] State0 Indicates support for A32 instruction set. This value is:
0x1
A32 instruction set implemented.
Table 4-155 ID_PFR0 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0001 000
To Next Page
Loading...
