ARM Cortex-A53 MPCore - Page 492

Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-38
ID021414 Non-Confidential
0xE0 - - - Attributable Performance Impact Event.
Counts every cycle that the DPU IQ is
empty and that is not because of a recent
micro-TLB miss, instruction cache miss
or pre-decode error.
0xE1 - - - Attributable Performance Impact Event.
Counts every cycle the DPU IQ is empty
and there is an instruction cache miss
being processed.
0xE2 - - - Attributable Performance Impact Event.
Counts every cycle the DPU IQ is empty
and there is an instruction micro-TLB
miss being processed.
0xE3 - - - Attributable Performance Impact Event.
Counts every cycle the DPU IQ is empty
and there is a pre-decode error being
processed.
0xE4 - - - Attributable Performance Impact Event.
Counts every cycle there is an interlock
that is not because of an Advanced
SIMD or Floating-point instruction, and
not because of a load/store instruction
waiting for data to calculate the address
in the AGU.
Stall cycles because of a stall in Wr,
typically awaiting load data, are
excluded.
0xE5 - - - Attributable Performance Impact Event.
Counts every cycle there is an interlock
that is because of a load/store instruction
waiting for data to calculate the address
in the AGU.
Stall cycles because of a stall in Wr,
typically awaiting load data, are
excluded.
0xE6 - - - Attributable Performance Impact Event.
Counts every cycle there is an interlock
that is because of an Advanced SIMD or
Floating-point instruction.
Stall cycles because of a stall in the Wr
stage, typically awaiting load data, are
excluded.
0xE7 - - - Attributable Performance Impact Event
Counts every cycle there is a stall in the
Wr stage because of a load miss.
Table 12-28 PMU events (continued)
Event
number
Event mnemonic
PMU event bus
(to external)
PMU event bus
(to trace)
Event name