ARM Cortex-A53 MPCore - Page 491

Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-37
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0x17 L2D_CACHE_REFILL [21] [21] L2 Data cache refill.
0x18 L2D_CACHE_WB [22] [22] L2 Data cache Write-Back.
0x19 BUS_ACCESS - - Bus access.
0x1A MEMORY_ERROR - - Local memory error.
0x1D BUS_CYCLES - - Bus cycle.
0x1E CHAIN - - Odd performance counter chain mode.
0x60 BUS_ACCESS_LD - - Bus access - Read.
0x61 BUS_ACCESS_ST - - Bus access - Write.
0x7A BR_INDIRECT_SPEC - - Branch speculatively executed - Indirect
branch.
0x86 EXC_IRQ - - Exception taken, IRQ.
0x87 EXC_FIQ - - Exception taken, FIQ.
0xC0 - - - External memory request.
0xC1 - - - Non-cacheable external memory
request.
0xC2 - - - Linefill because of prefetch.
0xC3 - - - Instruction Cache Throttle occurred.
0xC4 - - - Entering read allocate mode.
0xC5 - - - Read allocate mode.
0xC6 - - - Pre-decode error.
0xC7 - - - Data Write operation that stalls the
pipeline because the store buffer is full.
0xC8 - - - SCU Snooped data from another CPU
for this CPU.
0xC9 - - - Conditional branch executed.
0xCA - - - Indirect branch mispredicted.
0xCB - - - Indirect branch mispredicted because of
address miscompare.
0xCC - - - Conditional branch mispredicted.
0xD0 - [23] [23] L1 Instruction Cache (data or tag)
memory error.
0xD1 - [24] [24] L1 Data Cache (data, tag or dirty)
memory error, correctable or
non-correctable.
0xD2 - [25] [25] TLB memory error.
Table 12-28 PMU events (continued)
Event
number
Event mnemonic
PMU event bus
(to external)
PMU event bus
(to trace)
Event name