System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-13
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4.2.13 AArch64 address registers
Table 4-12 shows the address translation register in AArch64 state.
Table 4-12 AArch64 address translation register
Name Type Reset Width Description
PAR_EL1 RW UNK 64 Physical Address Register, EL1 on page 4-112
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