ARM Cortex-A53 MPCore - Page 259

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-198
ID021414 Non-Confidential
There is one copy of this register that is used in both Secure and
Non-secure states.
Bits in the NSACR control Non-secure access to the CPACR fields. See
the field descriptions cp10 and cp11.
Attributes CPACR is a 32-bit register.
Figure 4-100 shows the CPACR bit assignments.
Figure 4-100 CPACR bit assignments
Table 4-195 shows the CPACR bit assignments.
31 24 23
22
21
20 19 0
RES 0 cp11 cp10 RES 0
30
ASEDIS
Table 4-195 CPACR bit assignments
Bits Name Function
[31] ASEDIS Disable Advanced SIMD Functionality:
0 Does not cause any instructions to be UNDEFINED. This is the reset value.
1 All instruction encodings that are part of Advanced SIMD, but that are not floating-point
instructions, are UNDEFINED.
If Advanced SIMD and Floating-point are not implemented, this bit is
RES0.
[30:24] - Reserved,
RES0.
[23:22]
cp11
ab
Defines the access rights for CP11, that control the Advanced SIMD and Floating-point features. Possible values
of the fields are:
0b00 Access denied. Any attempt to access Advanced SIMD and Floating-point registers or
instructions generates an Undefined Instruction exception. This is the reset value.
0b01 Access at EL1 only. Any attempt to access Advanced SIMD and Floating-point registers or
instructions from software executing at EL0 generates an Undefined Instruction exception.
0b10 Reserved.
0b11 Full access.
If Advanced SIMD and Floating-point are not implemented, this field is
RES0.
[21:20]
cp10
a
Defines the access rights for CP10, that control the Advanced SIMD and Floating-point features. Possible values
of the fields are:
0b00 Access denied. Any attempt to access Advanced SIMD and Floating-point registers or
instructions generates an Undefined Instruction exception. This is the reset value.
0b01 Access at EL1 only. Any attempt to access Advanced SIMD and Floating-point registers or
instructions from software executing at EL0 generates an Undefined Instruction exception.
0b10 Reserved.
0b11 Full access.
If Advanced SIMD and Floating-point are not implemented, this bit is
RES0.
[19:0] - Reserved,
RES0.
a. The Floating-point and Advanced SIMD features controlled by these fields are:
Floating-point instructions.
Advanced SIMD instructions, both integer and floating-point.
Advanced SIMD and Floating-point registers D0-D31 and their views as S0-S31 and Q0-Q15.
FPSCR, FPSID, MVFR0, MVFR1, MVFR2, FPEXC system registers.