System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-195
ID021414 Non-Confidential
To access the SCTLR:
MRC p15, 0, <Rt>, c1, c0, 0 ; Read SCTLR into Rt
MCR p15, 0, <Rt>, c1, c0, 0 ; Write Rt to SCTLR
[11] - Reserved, RES1
[10:9] - Reserved,
RES0
[8] SED SETEND Disable:
0
The SETEND instruction is available.
1
The SETEND instruction is UNALLOCATED.
[7] ITD IT Disable:
0
The IT instruction functionality is available.
1
All encodings of the IT instruction with hw1[3:0]!=1000 are UNDEFINED and treated as
unallocated. All encodings of the subsequent instruction with the following values for hw1 are
UNDEFINED (and treated as unallocated):
11xxxxxxxxxxxxxx
All 32-bit instructions, B(2), B(1), Undefined, SVC, Load/Store multiple
1x11xxxxxxxxxxxx
Miscellaneous 16-bit instructions
1x100xxxxxxxxxxx
ADD Rd, PC, #imm
01001xxxxxxxxxxx
LDR Rd, [PC, #imm]
0100x1xxx1111xxx
ADD(4),CMP(3), MOV, BX pc, BLX pc
010001xx1xxxx111
ADD(4),CMP(3), MOV
[6] THEE
RES0
[5] CP15BEN CP15 barrier enable.
0
CP15 barrier operations disabled. Their encodings are UNDEFINED.
1
CP15 barrier operations enabled.
[4:3] - Reserved,
RES1.
[2] C Cache enable. This is a global enable bit for data and unified caches:
0
Data and unified caches disabled, this is the reset value.
1
Data and unified caches enabled.
[1] A Alignment check enable. This is the enable bit for Alignment fault checking:
0
Alignment fault checking disabled, this is the reset value.
1
Alignment fault checking enabled.
[0] M MMU enable. This is a global enable bit for the MMU stage 1 address translation:
0
EL1 and EL0 stage 1 MMU disabled.
1
EL1 and EL0 stage 1 MMU enabled.
Table 4-193 SCTLR bit assignments (continued)
Bits Name Function
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